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 N-CHANNEL 55V - 0.0060 - 80A D2PAK/TO-220 STripFETTM II POWER MOSFET
TYPE STP85NF55L STB85NF55L
s s s
STB85NF55L STP85NF55L
VDSS 55 V 55 V
RDS(on) <0.008 <0.008
ID 80 A 80 A
TYPICAL RDS(on) = 0.0060 LOW THRESHOLD DRIVE LOGIC LEVEL DEVICE
3 1
3 1 2
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC CONVERTERS s AUTOMOTIVE ENVIRONMENT
Ordering Information
SALES TYPE STP85NF55L STB85NF55L STB85NF55LT4 MARKING P85NF55L B85NF55L B85NF55L
D2PAK TO-263 (Suffix "T4")
TO-220
ADD SUFFIX "T4" FOR ORDERING IN TAPE & REEL
INTERNAL SCHEMATIC DIAGRAM
PACKAGE TO-220 D2PAK D2PAK
PACKAGING TUBE TUBE TAPE & REEL
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID(*) ID IDM (**) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 55 55 15 80 80 320 300 2.0 10 980 -55 to 175 Unit V V V A A A W W/C V/ns mJ C
(*) Current Limited by Package. (**) Pulse width limited by safe operating area. September 2002
1) ISD 80A, di/dt 300A/s, VDD V (BR)DSS, Tj TJMAX (2) Starting T j = 25 oC, ID = 40A, VDD = 30V
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STB85NF55L STP85NF55L
THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 0.5 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 15 V Min. 55 1 10 100 Typ. Max. Unit V A A nA
ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 5 V ID = 250 A ID = 40 A ID = 40 A Min. 1 Typ. 1.6 0.0060 0.008 Max. 2.5 0.008 0.01 Unit V
DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15V ID = 40 A Min. Typ. 130 4050 860 300 Max. Unit S pF pF pF
VDS = 25V f = 1 MHz VGS = 0
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ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 40 A VDD = 27.5 V VGS = 5 V RG = 4.7 (Resistive Load, Figure 3) VDD=27.5V ID=80A VGS=5V (see test circuit, Figure 4) Min. Typ. 35 165 80 20 45 110 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 40 A VDD = 27.5 V VGS = 5 V RG = 4.7, (Resistive Load, Figure 3) Min. Typ. 70 55 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A VGS = 0 80 240 6 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns nC A
ISD = 80 A di/dt = 100A/s Tj = 150C VDD = 20 V (see test circuit, Figure 5)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature.
.
.
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STB85NF55L STP85NF55L D2PAK MECHANICAL DATA
DIM. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 mm. MIN. 4.4 2.49 0.03 0.7 1.14 0.45 1.21 8.95 7.6 10 8.1 4.88 15 1.27 1.4 2.4 0.3 0 0.4 8.5 8 TYP. MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 8.4 10.4 8.9 5.28 15.85 1.4 1.75 3.2 0.5 8 MIN. 0.173 0.098 0.001 0.028 0.045 0.018 0.048 0.352 0.299 0.394 0.318 0.192 0.591 0.050 0.055 0.094 0.012 0 0.016 0.334 0.315 inch. TYP. TYP. 0.181
0.106
0.009 0.037 0.067 0.024 0.054 0.368 0.330 0.409 0.350 0.208 0.624 0.055 0.069 0.126 0.019 8
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STB85NF55L STP85NF55L TO-220 MECHANICAL DATA
DIM. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA 0.49 0.61 1.14 1.14 4.95 2.40 10 16.10 13 2.65 15.25 6.20 3.50 3.75 16.40 mm. MIN. 4.4 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.70 10.40 16.73 14 2.95 15.75 6.60 3.93 3.85 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.633 0.511 0.104 0.600 0.244 0.137 0.147 0.645 TYP. MAX. 4.6 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 0.658 0.551 0.116 0.620 0.260 0.154 0.151 inch. TYP. TYP. 0.181 0.051 0.107
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STB85NF55L STP85NF55L
D2PAK FOOTPRINT
TUBE SHIPMENT (no suffix)*
TAPE AND REEL SHIPMENT (suffix "T4")*
REEL MECHANICAL DATA
DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 BASE QTY 1000 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.795 0.960 3.937 1.197 BULK QTY 1000 1.039 0.520 MIN. inch MAX. 12.992
TAPE MECHANICAL DATA
DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 0.35 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 MIN. 0.413 0.618 0.059 0.062 0.065 0.449 0.189 0.153 0.468 0075 1.574 .0.0098 0.933 0.0137 0.956 inch MAX. 0.421 0.626 0.063 0.063 0.073 0.456 0.197 0.161 0.476 0.082
* on sales type
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STB85NF55L STP85NF55L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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